FIG. 1A is a schematic circuit diagram illustrating a conventional non-volatile memory. FIG. 1B is a schematic circuit diagram illustrating a memory cell of a MTP memory. FIG. 1C is a schematic circuit diagram illustrating a memory cell of an OTP memory. As shown in FIG. 1A, the non-volatile memory comprises a memory array, a row decoder 110, a column decoder 130, a write buffer 150 and a sensing circuit 140. The row decoder 110 is connected with m word lines WL1˜WLm. The column decoder 130 is connected with n bit lines BL1˜BLn. The memory array comprises m×n memory cells C11˜Cmn. Moreover, the memory array is connected with the m word lines WL1˜WLm, the n bit lines BL1˜BLn and a voltage source V1.
Generally, the working state of the memory array may be at least divided into a program cycle and a read cycle. During the program cycle, a selected memory cell is determined by the row decoder 110 and the column decoder 130, and the voltage value of the voltage source V1 is correspondingly adjusted. Consequently, a program action of the selected memory cell is performed. Similarly, under control of the row decoder 110 and the column decoder 130, the program actions of more selected memory cells are sequentially performed. After the program actions of all selected memory cells are completed, the program cycle is ended.
After the program cycle, each memory cell is in either a first storing state (e.g. the storing state “0”) or a second storing state (e.g. the storing state “1”).
During the read cycle, a selected memory cell is determined by the row decoder 110 and the column decoder 130, and the voltage value of the voltage source V1 is correspondingly adjusted. Consequently, a read action of the selected memory cell is performed, and the storing state of the selected memory cell is determined. Similarly, under control of the row decoder 110 and the column decoder 130, the read actions of more selected memory cells are sequentially performed. After the read actions of all selected memory cells are completed, the read cycle is ended.
As shown in FIG. 1A, the column decoder 130 comprises a column decoding circuit 132 and a switching circuit 134. The column decoder 130 is operated according to a column control signal set Y[n:1] and a switch control signal set Sw[2:1]. The column control signal set Y[n:1] contains n column control signals from the first column control signal Y1 to the n-th column control signal Yn. The switch control signal set Sw[2:1] contains a first switch control signal Sw1 and a second switch control signal Sw2.
The column decoding circuit 132 comprises n switch transistors My1˜Myn. According to the column control signal set Y[n:1], one of the n switch transistors My1˜Myn is in a close state but the others of the n switch transistors My1˜Myn are in an open state.
The switching circuit 134 comprises two switch transistors Mpgm and Mrd. According to the switch control signal set Sw[2:1], one of the two switch transistors Mpgm and Mrd is in the close state but the other switch transistor is in the open state.
During the program cycle, the row decoder 110 activates a word line to determine a selected row of n memory cells. Moreover, according to the column control signal set Y[n:1], the column decoding circuit 132 of the column decoder 130 determines a selected memory cell from the selected row of n memory cells. Then, according to the switch control signal set Sw[2:1], the switching circuit 134 of the column decoder 130 controls the switch transistors Mpgm and Mrd to be in the close state and the open state, respectively. Consequently, during the program cycle, a cell current generated by the selected memory cell flows to the write buffer 150.
During the read cycle, the row decoder 110 activates a word line to determine a selected row of n memory cells. Moreover, according to the column control signal set Y[n:1], the column decoding circuit 132 of the column decoder 130 determines a selected memory cell from the selected row of n memory cells. Then, according to the switch control signal set Sw[2:1], the switching circuit 134 of the column decoder 130 controls the switch transistors Mpgm and Mrd to be in the open state and the close state, respectively. Consequently, during the read cycle, the cell current generated by the selected memory cell flows to the sensing circuit 140. Then, the sensing circuit 140 determines the storing state of the selected memory cell according to the cell current.
Hereinafter, a process of programming the memory cell C22 and a process of reading the memory cell C22 will be illustrated as examples. During the program cycle, the row decoder 110 activates the word line WL2 to determine a selected row of n memory cells C21˜C2n. Moreover, if the second column switch signal Y2 is activated but the other column switch signals Y1 and Y3˜Yn are inactivated, only the switch transistor My2 is in the close state but the other switch transistors My1 and My3˜Myn are in the open state under control of the column decoding circuit 132 of the column decoder 130. Consequently, the memory cell C22 is the selected memory cell. Moreover, since the first switch control signal Sw1 is activated and the second switch control signal Sw2 is inactivated, the switching circuit 134 of the column decoder 130 controls the switch transistors Mpgm and Mrd to be in the close state and the open state, respectively. Consequently, during the program cycle, the cell current generated by the selected memory cell C22 flows to the write buffer 150. Meanwhile, the program action of the selected memory cell C22 is completed.
During the read cycle, the row decoder 110 activates the word line WL2 to determine a selected row of n memory cells C21˜C2n. Moreover, if the second column switch signal Y2 is activated but the other column switch signals Y1 and Y3˜Yn are inactivated, only the switch transistor My2 is in the close state but the other switch transistors My1 and My3˜Myn are in the open state under control of the column decoding circuit 132 of the column decoder 130. Consequently, the memory cell C22 is the selected memory cell. Moreover, since the first switch control signal Sw1 is activated and the second switch control signal Sw2 is inactivated, the switching circuit 134 of the column decoder 130 controls the switch transistors Mpgm and Mrd to be in the open state and the close state, respectively. Consequently, during the read cycle, the cell current generated by the selected memory cell C22 flows to the sensing circuit 140. Then, the sensing circuit 140 determines the storing state of the selected memory cell according to the cell current.
Generally, according to the number of times the non-volatile memory is programmed, the non-volatile memories may be classified into a multi-time programming memory (also referred as a MTP memory) and a one time programming memory (also referred as an OTP memory). The above column decoder 130 may be applied to the MTP memory or the OTP memory.
The configuration of the memory cell for the MTP memory, is shown in FIG. 1B. As shown in FIG. 1B, the memory cell comprises a floating gate transistor M. A control gate of the floating gate transistor M is connected with the word line WL. The drain terminal of the floating gate transistor M is connected with the bit line BL. The source terminal of the floating gate transistor M is connected with the voltage source V1.
During the program cycle, the storing state of the memory cell is determined according to the amount of the hot carriers stored in the floating gate of the floating gate transistor M. For example, if the hot carriers are injected into the floating gate of the floating gate transistor M, the memory cell has the first storing state (e.g. the storing state “0”). Whereas, if no hot carriers are injected into the floating gate of the floating gate transistor M, the memory cell has the second storing state (e.g. the storing state “1”).
The configuration of the memory cell for the OTP memory is shown in FIG. 1C. As shown in FIG. 1C, the memory cell comprises a select transistor T and a capacitor C, which are connected with each other in series. A control gate of the select transistor T is connected with the word line WL. A first drain/source terminal is connected with the bit line BL. A second drain/source terminal is connected with a first terminal of the capacitor C. A second terminal of the capacitor C is connected with the voltage source V1.
During the program cycle, if the dielectric layer of the capacitor C is ruptured by a large current, the capacitor C is turned into a resistor. Under this circumstance, the memory cell has the first storing state (e.g. the storing state “0”). Whereas, if the dielectric layer of the capacitor C is not ruptured by the large current, the memory cell has the second storing state (e.g. the storing state “1”).
The configurations of the memory cells shown in FIGS. 1B and 1C are illustrated herein for purpose of illustration and description only. It is noted that the column decoder 130 may be applied to the MTP memory or the OTP memory with any other appropriate configurations of memory cells.
Generally, during the program cycle, the magnitude of the cell current generated by the selected memory cell is very large. Consequently, the switch transistors My1˜Myn of the column decoding circuit 132 should have large sizes. For example, each of the switch transistors My1˜Myn is designed to have a width of 36 μm and a channel length of 0.25 μm. Since the sizes of the switch transistors My1˜Myn are very large, the voltage drop across each of the switch transistors My1˜Myn is not very high while the cell current flows therethrough.
Moreover, during the read cycle, a charging action of the selected memory cell is performed by the sensing circuit 140 according to the cell current generated by the selected memory cell, and the storing state of the selected memory cell is determined by the sensing circuit 140 according to the magnitude of a charging voltage. However, since the sizes of the switch transistors My1˜Myn are very large, the time period of performing the read action will be extended.
Generally, the larger-sized switch transistor has a larger parasitic capacitance. Under this circumstance, the RC time constant of the circuitry is larger, and the charging voltage is slowly increased. Consequently, the sensing circuit 140 is unable to determine the storing state of the selected memory cell in a short time. In other words, because of the column decoder 130, the read sensing speed of the sensing circuit 140 is usually unsatisfied.